Computer code includes instructions that are organized in a particular order, and which are executed by a processor, such as a central processing unit (CPU), to perform desired functionality. It is usually presumed by the developer of the computer code that the instructions thereof will be executed in the order in which the instructions are presented. However, some types of processors and compilers optimize computer code to improve execution performance, and this optimization can result in out-of-order execution of the instructions.
While generally such out-of-order execution is not problematic, it can cause unpredictable behavior, particularly with respect to load and store instructions that are executed in relation to memory locations. If the contents of a memory location are loaded before desired contents are stored at this memory location, when it is expected that the desired contents will be stored before they are subsequently loaded, problems can arise such that the computer code does not perform its desired functionality. Therefore, processors and compilers can include mechanisms by which to enforce ordering constraints in the executions of instructions within computer code.
One such mechanism is a memory barrier instruction, which is also referred to as a memory barrier instruction, a membar, a memory fence, or a fence instruction. A memory barrier instruction prohibits instructions, such as load and store instructions, located after the memory barrier from being executed prior to instructions, such as load and store instructions, located before the memory barrier. For example, if a store instruction has to be executed prior to a load instruction, then a memory barrier instruction can be inserted somewhere between the store instruction and the load instruction. As such, unpredictable behavior in computer code execution can be avoided.